The present invention relates to integrated circuit fabrication and to the formation of interconnect pads on an integrated circuit device. Specific embodiments of the invention relate to a method for forming an interconnect pad having a screen printed conductive layer. Methods of the present invention are of use in forming a screen printed conductive layer on a variety of integrated circuit metal pads, such as copper, aluminum, and gold pads among others.
The semiconductor industry continues to produce integrated circuits (ICs) of increasing complexity and increasing density. The increased complexity of some of these integrated circuits has in turn resulted in an increased number of interconnect pads on the circuit chips. Each pad can be used for conventional wire bonding or flip chip bonding. At the same time, the increased density of the chips has driven the interconnect pad pitch downward. The combination of these two trends has been a significant increase in the interconnect pad density needed to connect the chips to printed wiring board substrates that interface with external devices and/or interconnect the chips to other integrated circuit devices.
Integrated circuit interconnect pads are typically formed in multi-step processes in which one or more metal layers, commonly referred to as under-bump metalization layers, are sputtered onto an underlying terminal metalization pad. Sputtering is a relatively costly process that includes numerous process steps that are carried out in a vacuum processing chamber. FIGS. 1, 2, 3, 4, 5, 6, and 7 show a typical time ordered sequence of steps of a typical method for forming a solder ball 195 and an under-bump metalization layer 140 (or simply under-bump metalization) on a terminal metalization pad 115 of an integrated circuit 100. Under-bump metalization 140 in combination with terminal metalization pad 115 form an interconnect pad 120 of the integrated circuit 100. Metal layer 110 is deposited on terminal metalization pad 115 and passivation layer 125 via sputtering or other process as shown in FIG. 1. The sputtered metal may include titanium, nickel-vanadium, copper, or other metals. Unwanted portions 135 of metal layer 110 are removed (see FIG. 2), for example, by wet or dry etching. To etch portions 135, a photoresist layer 140 is formed over metal layer 110. The photoresist layer is then exposed and developed to reveal portions 135, which are then etched resulting in the structure shown in FIG. 3. The remaining photoresist is subsequently removed to expose the remaining portion of the metal layer, referred to as under-bump metalization 140. The under-bump metalization and terminal metalization pad form an interconnect pad 120 through which the integrated circuit is electrically coupled to an integrated circuit package (not shown) and/or other integrated circuits (not shown). Subsequent to forming interconnect pad 120, a seed layer 150 is formed over passivation layer 125 and under-bump metalization 140, FIG. 4. A mask 160 is formed over the seed layer 150 and a solder paste layer 165 is then electroplated onto the seed layer, FIG. 5. Mask 160 is subsequently removed (see FIG. 6) and solder paste layer 165 is then reflowed to form solder bump 195 (see FIG. 7). Because of the relatively large number of process steps used to form interconnect pad 120, and because the process steps tend to be costly, for example, because some are carried out in a vacuum processing chamber, the process of forming interconnect pads is relatively costly and increases the price of the resultant integrated circuit die. Moreover, the numerous processing steps also tend to make integrated circuit fabrication times relatively long.
Accordingly, the semiconductor industry continues to strive to reduce the number of steps used to form integrated circuit interconnect pads and to reduce the duration and cost of the steps.